(1) Field of the Invention
The present invention relates generally to a method of forming a thick field oxide layer of a semiconductor substrate, and more particularly to a method of increasing the thickness of the field oxide layer by forming a silicon dioxide on the field oxide layer. The invention is illustrated in an example with regard to a method of increasing the thickness of the field oxide layer to improve the Gate Coupling Ratio (GCR) with regard to the manufacture of a Read Only Memory (ROM), more particularly to the manufacture of a Flash Electrically Erasable Programmable Read Only Memory (Flash EEPROM).
(2) Description of the Prior Art
A microcircuit can be described as an "ensemble of active and passive components, interconnected within a monolithic block of semiconductor material." Thus the first requirement is to devise schemes for fabricating components that are electrically isolated from each other in order to allow design flexibility. One of the numerous different approaches been in use today is the localized oxidation of silicon (LOCOS) which is specific to silicon microcircuits. In the LOCOS process, a field oxide layer is formed onto a silicon substrate. The field oxide layer can isolate components from each other for their independent operation.
In general, the field oxide layer is formed at exposed regions of a silicon substrate by using a method of thermal oxidation. One of the technological problems which arise during the application of LOCOS is "bird's beak", which is a lateral extension of the field oxide into the active area of the device. This effect leads to predictions that LOCOS isolation would decrease the active area of the device and increase difficulties in the semiconductor processing.
The thicker the field oxide is, the better the isolation between devices is. However, one of the parameters upon which the length of the bird's beak depends is the thickness of the isolation field oxide. Therefore, increasing the thickness of isolation field oxide without limiting the size or area of the active device regions can not only improve the isolation between devices but also increase the range of applications on a Read Only Memory (ROM).
In the fabrication of a ROM, particularly an EEPROM, it is often necessary to fabricate a storage cell that retains data after the applied power is turned off, that is, a storage cell having almost permanent data characteristics. The storage cells are generally mass data storage files where each cell corresponds to the presence or absence of a stored charge on a floating gate of a storage cell transistor. Specifically, the storage cell includes at least two conducting layers, i.e., one conducting layer is the control gate for control of the cell operation. The floating gate is formed on a thin gate oxide formed on the substrate. The control gate is located above the floating gate, and the control gate and floating gate are isolated from each other by a thin dielectric layer known as an "interpoly oxide", which may typically be composed of oxide/nitride/oxide (ONO). In some typical EEPROMs, data is programmed into the cells by applying a high voltage to the control gate to inject hot electrons (or tunnel electrons in some devices) into the floating gate. The process of programming data is often called coding. In coding, the charge is transferred from the silicon substrate through the thin gate oxide layer to the floating gate. The interface area A2 (FIG. 1) between the floating gate and the control gate are related to the Gate Coupling Ratio (GCR) of the EEPROM. A larger interface area between floating gate and control gate can get a higher the Gate Coupling Ratio (GCR) of the EEPROM. Thus, the required voltage of driving electrons for programming and erasing data would be lowered.
In EEPROMs, especially for flash EEPROMs, it is generally critical to grow a high-quality, thin gate oxide (used as a tunneling oxide) in the storage cell and (used as a thin gate oxide) in some transistors in the periphery of the storage cell region in order to provide high driving capability for higher speed. Controlling the thickness of the thin gate oxide is crucial, especially since design rules for devices with gates are becoming increasingly smaller and require thinner gate oxides. Because high-voltage supplies are used, thicker gate oxides at the periphery of the storage cell region are needed to maintain device quality and reliability after long-term high voltage stress from the high voltage (e.g., up to or greater than .+-.12 V) generated through a pumping circuit for storage cell coding and/or erase. Therefore, implementing larger field oxide thickness in EEPROM devices is an important aspect of the fabrication of high performance devices.
FIG. 1 shows a cross-section view of an EEPROM structure formed according to conventional steps. The EEPROM is made using a LOCOS process. The field isolation oxide layer is generally made by forming a thickness of silicon dioxide 111 using an oxidation process, i.e., thermal treatment, overlying a silicon substrate 101. Each of the isolation structures includes active device regions between the isolation structures. Next, a thickness of silicon dioxide (not shown), which is made for a gate oxide layer, is formed on the surface of the active device regions using an oxidation process. A first polysilicon layer 131 as the floating gate of the ROM is formed onto the gate oxide layer. Then, a second polysilicon layer 141 as the control gate of the ROM is formed overlying the field oxide 111 and the first polysilicon layer 131.
Referring to FIG. 1, the interface area A2 between the first polysilicon layer 131 and the second polysilicon layer 141 depends upon the surface area of the first polysilicon layer 131. If the thickness of the field oxide layer 111 is increased but the length of the field oxide 111, then A2 can be increased effectively and the interface area A1 between gate oxide and silicon substrate can be maintained. Thus, the Gate Coupling Ratio (GCR) of the EEPROM would be improved without enlarging bird's beak, and the operating voltage of the EEPROM would be lowered.
From the above, it is seen that the technique of the present invention for improving the isolation between integrated circuit devices by increasing the thickness of field oxide layer and simultaneously increasing the GCR to lower the operation voltage of devices is highly desired.